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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tusb544 sllsez0b ? april 2017 ? revised may 2017 tusb544 usb type-c ? 8.1 gbps multi-protocol linear redriver 1 1 features 1 ? protocol agnostic reversible 4 channel linear redriver supporting up to 8.1 gbps ? supports usb type-c with usb 3.1 gen1 and displayport 1.4 as alternate mode. ? supports processors with usb 3.1 and displayport mux integrated for type-c applications ? supports signal conditioning inside type-c cable ? cross-point mux for sbu signals ? gpio and i 2 c control for channel direction and equalization ? advanced power management by monitoring usb power states and snooping dp link training ? linear equalization up to 11 db at 4.05 ghz ? configuration through gpio or i 2 c ? hot-plug capable ? single 3.3 v supply ? industrial temperature: ? 40 o c to 85 o c TUSB544I ? commercial temperature: 0 o c to 70 o c tusb544 ? 4 mm 6 mm, 0.4 mm pitch, 40-pin qfn package 2 applications ? tablets ? notebooks ? desktops ? docking stations 3 description the tusb544 is a usb type-c alt mode redriver switch supporting data rates up to 8.1 gbps this protocol-agnostic linear redriver is capable of supporting usb type-c alt mode interfaces including displayport. the tusb544 provides several levels of receive linear equalization to compensate for cable and board trace loss due to inter symbol interference (isi). operates on a single 3.3 v supply and comes in a commercial and industrial temperature range. all four lanes of the tusb544 are reversible making it a versatile signal conditioner that can be used in many applications. device information (1) part number package body size (nom) tusb544 wqfn (40) 4.00 mm x 6.00 mm TUSB544I (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematic usb/dp/ custom source tusb544 sbu1 sbu2 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control hpd ctl flip 0 1 d+/- utx1 utx2 urx1 urx2 tx1 tx2 rx1 rx2 auxp auxn auxp auxn sbu1 sbu2 tx1 tx2 rx1 rx2 hpdin copyright ? 2017, texas instruments incorporated type t c receptacle tusb544 productfolder ordernow technical documents tools & software support &community
2 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 6 6.5 power supply characteristics ................................... 6 6.6 dc electrical characteristics .................................... 6 6.7 ac electrical characteristics ..................................... 7 6.8 timing requirements ................................................ 9 6.9 switching characteristics .......................................... 9 6.10 typical characteristics .......................................... 12 7 detailed description ............................................ 15 7.1 overview ................................................................. 15 7.2 functional block diagram ....................................... 16 7.3 feature description ................................................. 17 7.4 device functional modes ........................................ 18 7.5 programming .......................................................... 29 7.6 register maps ........................................................ 30 8 application and implementation ........................ 39 8.1 application information ............................................ 39 8.2 typical application ................................................. 39 8.3 system examples .................................................. 43 9 power supply recommendations ...................... 50 10 layout ................................................................... 51 10.1 layout guidelines ................................................. 51 10.2 layout example .................................................... 51 11 device and documentation support ................. 52 11.1 documentation support ....................................... 52 11.2 receiving notification of documentation updates 52 11.3 community resources .......................................... 52 11.4 trademarks ........................................................... 52 11.5 electrostatic discharge caution ............................ 52 11.6 glossary ................................................................ 52 12 mechanical, packaging, and orderable information ........................................................... 52 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision a (april 2017) to revision b page ? added a min value of 0.5 pf to c i_i2c in the dc electrical characteristics table .................................................................. 7 ? changed v rx-dc-cm , deleted the min and max values and added typ = 0 v in the ac electrical characteristics table...... 7 ? changed eq ss description from: " receiver equalization " to: " receiver equalization at maximum setting " in the ac electrical characteristics table ............................................................................................................................................... 7 ? changed eq ss from: max = 9.8 db to: max = 9 db in the ac electrical characteristics table ......................................... 7 ? changed v tx-dc-cm , deleted the min and max values and added typ = 1.75 v in the ac electrical characteristics table . 7 ? changed rl tx-diff from: typ = -14 db to: typ = -13 db in the ac electrical characteristics table................................... 8 ? changed rl tx-cm from: typ = -13 db to: typ = -11 db in the ac electrical characteristics table .................................... 8 ? changed g lf from: max = 2.5 db to: max = 1 db in the ac electrical characteristics table ............................................ 8 ? changed v ic , deleted the min and max values and added typ = 0 v in the ac electrical characteristics table ............... 8 ? changed the eq dp entry in the ac electrical characteristics table ....................................................................................... 8 ? changed v tx(dc-cm) , deleted the min and max values and added typ = 1.75 v in the ac electrical characteristics table 8 ? changed the t idleexit_disc value from: typ = 10 s to typ = 15 ms in the timing requirements table .............................. 9 ? changed the t ctl1_debounce value from: min = 2 ms to: min = 3 ms in the switching characteristics table ..................... 9 changes from original (april 2017) to revision a page ? changed sub1, sub2, auxn, and auxp pin labels on the sink side of figure 45 ............................................................ 47 ? changed sub1, sub2, auxn, and auxp pin labels on the sink side of figure 46 ............................................................ 47
3 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 5 pin configuration and functions rnq package 40-pin (wqfn) top view pin functions pin i/o description no. name 1 vcc p 3.3 v power supply 2 ueq1/a1 4 level i this pin along with ueq0 sets the high-frequency equalizer gain for upstream facing urx1, urx2, utx1, utx2 receivers. up to 9.4 db of eq available. when i2c_en !=0, this pin will also set tusb544 i2c address. refer to table 10 . 3 cfg0 4 level i cfg0. this pin along with cfg1 will select vod linearity range and dc gain for all the downstream and upstream channels. refer to table 8 for vod linearity range and dc gain options. 4 cfg1 4 level i cfg1. this pin along with cfg0 will set vod linearity range and dc gain for all the downstream and upstream channels. refer to table 8 for vod linearity range and dc gain options. 5 swap 2 level i this pin swaps all the channel directions and eq settings of downstream facing and upstream facing data path inputs. 0 ? do not swap channel directions and eq settings (default) 1. ? swap channel directions and eq settings. 6 vcc p 3.3v power supply 7 slp_s0# 2 level i this pin when asserted low will disable receiver detect functionality. while this pin is low and tusb544 is in u2/u3, tusb544 will disable los and lfps detection circuitry and rx termination for both channels will remain enabled. if this pin is low and tusb544 is in disconnect state, the rx detect functionality will be disabled and rx termination for both channels will be disabled. 0 ? rx detect disabled 1 ? rx detect enabled (default) 8 dir0 2 level i this pin along with dir1 sets the data path signal direction format. refer to table 4 for signal direction formats. 9 urx2p diff i/o differential positive input/output for upstream facing rx2 port. 10 urx2n diff i/o differential negative input/output for upstream facing rx2 port. 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 12 11 10 9 8 7 ueq1/a1 vcc cfg0 25 28 26 27 36 35 34 33 32 31 30 29 37 38 39 40 dtx2p drx1p utx2p dir0 urx2p drx2p cfg1 utx1n utx1p dtx2n utx2n urx2n swap drx1n slp_s0# drx2n urx1n urx1p hpdin dtx1p dtx1n ueq0/a0 sbu2 sbu1 deq1 i2c_en vio_sel deq0 ctl0/sda flip/scl vcc vcc ctl1 auxp auxn thermal pad gnd vcc dir1
4 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin i/o description no. name 11 dir1 2 level i/o this pin along with dir0 sets the data path signal direction format. refer to table 4 for signal direction formats. 12 utx2p diff i/o differential positive input/output for upstream facing tx2 port. 13 utx2n diff i/o differential negative input/output for upstream facing tx2 port. 14 vio_sel 4 level i/o this pin selects i/o voltage levels for the gpio configuration pins and the i2c interface: 0 = 3.3-v configuration i/o voltage, 3.3-v i 2 c interface (default) r = 3.3-v configuration i/o voltage, 1.8-v i 2 c interface f = 1.8-v configuration i/o voltage, 3.3-v i 2 c interface 1 = 1.8-v configuration i/o voltage, 1.8-v i 2 c interface. 15 utx1n diff i/o differential negative input/output for upstream facing tx1 port. 16 utx1p diff i/o differential positive input/output for upstream facing tx1 port. 17 i2c_en 4 level i i2c programming or pin strap programming select. 0 = gpio mode (i 2 c disabled) r = ti test mode (i 2 c enabled) f = gpio mode, aux snoop disabled (i 2 c disabled) 1 = i2c enabled. 18 urx1n diff i/o differential negative input/output for upstream facing rx1 port. 19 urx1p diff i/o differential positive input/output for upstream facing rx1 port. 20 vcc p 3.3v power supply 21 flip/scl 2 level i (failsafe) when i2c_en= ? 0 ? this is flip control pin, otherwise this pin is i 2 c clock. 22 ctl0/sda 2 level i (failsafe) when i2c_en= ? 0 ? this is a usb3.1 switch control pin, otherwise this pin is i 2 c data. 23 ctl1 2 level i (pd) dp alt mode switch control pin. when i2c_en = ? 0 ? , this pin will enable or disable displayport functionality. otherwise displayport functionality is enabled and disabled through i2c registers. l = displayport disabled. h = displayport enabled. when i2c_en = 0, this pin is not used by device. 24 auxp i/o, cmos auxp. displayport aux positive i/o connected to the displayport source or sink through an ac coupling capacitor. in addition to ac coupling capacitor, this pin also requires a 100-k resistor to gnd between the ac coupling capacitor and the auxp pin if the tusb544 is used on the displayport source side, or a 1-m resistor to dp_pwr (3.3v) between the ac coupling capacitor and the auxp pin if tusb544 is used on the displayport sink side. this pin along with auxn is used by the tusb544 for aux snooping and is routed to sbu1/2 based on the orientation of the type-c plug. 25 auxn i/o, cmos auxn. displayport aux i/o connected to the displayport source or sink through an ac coupling capacitor. in addition to ac coupling capacitor, this pin also requires a 100-k resistor to dp_pwr (3.3v) between the ac coupling capacitor and the auxn pin if the tusb544 is used on the displayport source side, or a 1-m resistor to gnd between the ac coupling capacitor and the auxn pin if tusb544 is used on the displayport sink side. this pin along with auxp is used by the tusb544 for aux snooping and is routed to sbu1/2 based on the orientation of the type-c plug. 26 sbu2 i/o, cmos sbu2. when the tusb544 is used on the displayport source side, this pin should be dc coupled to the sbu2 pin of the type-c receptacle. when the tusb544 is used on the displayport sink side, this pin should be dc coupled to the sbu1 pin of the type-c receptacle. a 2-m resistor to gnd is also recommended. 27 sbu1 i/o, cmos sbu1. when the tusb544 is used on the displayport source side, this pin should be dc coupled to the sbu1 pin of the type-c receptacle. when the tusb544 is used on the displayport sink side, this pin should be dc coupled to the sbu2 pin of the type-c receptacle. a 2-m resistor to gnd is also recommended. 28 vcc p 3.3v power supply 29 deq1 4 level i this pin along with deq0 sets the high-frequency equalizer gain for downstream facing drx1, drx2, dtx1, dtx2 receivers. up to 11 db of eq available. 30 drx1p diff i/o differential positive input/output for downstream facing rx1 port. 31 drx1n diff i/o differential negative input/output for downstream facing rx1 port. 32 hpdin 2 level i (pd) when i2c_en = 0, this pin is an input for hot plug detect received from displayport sink. when hpdin is low for greater than 2ms, all displayport lanes are disabled and aux to sbu switch will remain closed. 33 dtx1p diff i/o differential positive input/output for downstream facing tx1 port. 34 dtx1n diff i/o differential negative input/output for downstream facing tx1 port. 35 ueq0/a0 4 level i this pin along with ueq1 sets the high-frequency equalizer gain for upstream facing urx1, urx2, utx1, utx2 receivers. up to 9.4 db of eq available. when i2c_en !=0, this pin will also set tusb544 ? s i2c address. refer to table 10 . 36 dtx2n diff i/o differential negative input/output for downstream facing tx2 port.
5 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin i/o description no. name 37 dtx2p diff i/o differential positive input/output for downstream facing tx2 port. 38 deq0 4 level i this pin along with deq1 sets the high-frequency equalizer gain for downstream facing urx1, urx2, utx1, utx2 receivers. up to 11 db of eq available. 39 drx2n diff i/o differential negative input/output for downstream facing rx2 port. 40 drx2p diff i/o differential positive input/output for downstream facing rx2 port. thermal pad gnd ground (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage v cc ? 0.3 4 v voltage range at any input or output pin differential voltage between positive and negative inputs ? 2.5 2.5 v voltage at differential inputs ? 0.5 v cc + 0.5 v cmos inputs ? 0.5 v cc + 0.5 v maximum junction temperature, t j 125 c storage temperature ,t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 6 kv charged-device model (cdm), per jedec specification jesd22- c101 (2) 1500 v 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v cc main power supply 3 3.3 3.6 v supply ramp requirement 100 ms v i2c supply that external resistors on sda and scl are pulled up to. 1.70 3.6 v v psn supply noise on v cc terminals 100 mv t a operating free-air temperature tusb544 0 70 c TUSB544I ? 40 85 c
6 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) tusb544 unit rnq (qfn) 40 pins r ja junction-to-ambient thermal resistance 37.6 c/w r jc(top) junction-to-case (top) thermal resistance 20.7 c/w r jb junction-to-board thermal resistance 9.5 c/w jt junction-to-top characterization parameter 0.2 c/w jb junction-to-board characterization parameter 9.4 c/w r jc(bot) junction-to-case (bottom) thermal resistance 2.3 c/w 6.5 power supply characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit p cc-active-usb average active power usb only link in u0 with gen1 data transmission. eq control pins = nc, k28.5 pattern at 5 gbps, v id = 1000 mv p-p ; vod linearity = 900 mv p-p ; ctl1 = l; ctl0 = h 297 mw p cc-active-usb-dp1 average active power usb + 2 lane dp link in u0 with gen1 data transmission. eq control pins = nc, k28.5 pattern at 5 gbps, v id = 1000 mv p-p ; vod linearity = 900 mv p-p ; ctl1 = h; ctl0 = h 578 mw p cc-active-usb-custom average active power usb + 2 channel custom alt mode link in u0 with gen1 data transmission. eq control pins = nc, k28.5 pattern at 5 gbps, v id = 1000 mv p-p ; vod linearity = 900 mv p-p ; ctl1 = h; ctl0 = h 578 mw p cc-active-dp average active power 4 lane dp only four active dp lanes operating at 8.1 gbps; eq control pins = nc, k28.5 pattern at 5 gbps, v id = 1000 mv p-p ; vod linearity = 900 mv p-p ; ctl1 = h; ctl0 = l; 564 mw p cc-nc-usb average power with no connection no gen1 device is connected to txp/txn; ctl1 = l; ctl0 = h; 2.5 mw p cc-u2u3 average power in u2/u3 link in u2 or u3 usb mode only; ctl1 = l; ctl0 = h; 2.0 mw p cc-shutdown device shutdown ctl1 = l; ctl0 = l; i2c_en = 0; 0.65 mw 6.6 dc electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit 4-state cmos inputs(ueq[1:0];deq[1:0], cfg[1:0], a[1:0], i2c_en, vio_sel) i ih high level input current v cc = 3.6 v in = 3.6 v 20 80 a i il low level input current v cc = 3.6 v; v in = 0 v ? 160 ? 40 a 4-level v th threshold 0 / r v cc = 3.3 v 0.55 v threshold r/ float v cc = 3.3 v 1.65 v threshold float / 1 v cc = 3.3 v 2.7 v r pu internal pull-up resistance 35 k r pd internal pull-down resistance 95 k 2-state cmos input (ctl0, ctl1, flip, hpdin, slp_s0#, swap, dir[1:0]). v ih high-level input voltage 0.7 v io 3.6 v v il low-level input voltage 0 0.3 v io v r pd internal pull-down resistance for ctl1 500 k ? i ih high-level input current v in = 3.6 v ? 25 25 a i il low-level input current v in = gnd, v cc = 3.6 v ? 25 25 a i 2 c control pins scl, sda
7 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated dc electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit v ih high-level input voltage i2c_en = 0 0.7 x v i2c 3.6 v v il low-level input voltage i2c_en = 0 0 0.3 x v i2c v v ol low-level output voltage i2c_en = 0; i ol = 3 ma 0 0.4 v i ol low-level output current i2c_en = 0; v ol = 0.4 v 20 ma i i_i2c input current on sda pin 0.1 x v i2c < input voltage < 3.3 v ? 10 10 a c i_i2c input capacitance 0.5 10 pf 6.7 ac electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit usb gen 1 differential receiver (utx1p/n, utx2p/n, drx1p/n, drx2p/n) v rx-diff-pp input differential peak-peak voltage swing linear dynamic range ac-coupled differential peak-to-peak signal measured post ctle through a reference channel 2000 mvpp v rx-dc-cm common-mode voltage bias in the receiver (dc) 0 v r rx-diff-dc differential input impedance (dc) present after a gen1 device is detected on receiver pins 72 120 r rx-cm-dc receiver dc common mode impedance present after a gen1 device is detected on receiver pins 18 30 z rx-high-imp-dc-pos common-mode input impedance with termination disabled (dc) present when no gen1 device is detected on receiver pins. measured over the range of 0-500mv with respect to gnd. 25 k v signal-det-diff-pp input differential peak-to-peak signal detect assert level at 5 gbps, no loss at the input, prbs7 pattern 80 mv v rx-idle-det-diff-pp input differential peak-to-peak signal detect de-assert level at 5 gbps, no loss at the input, prbs7 pattern 60 mv v rx-lfps-det-diff-pp low frequency periodic signaling (lfps) detect threshold below the minimum is squelched. 100 300 mv v rx-cm-ac-p peak rx ac common-mode voltage measured at package pin 150 mv c rx rx input capacitance to gnd at 2.5 ghz 0.5 1 pf rl rx-diff differential return loss 50 mhz ? 1.25 ghz at 90 ? 16 db 2.5 ghz at 90 ? 14 db rl rx-cm common-mode return loss 50 mhz ? 2.5 ghz at 90 ? 13 db eq ss receiver equalization at maximum setting ueq[1:0] and deq[1:0]. at 2.5 ghz 9 db usb gen 1 differential transmitter (dtx1p/n, dtx2p/n, urx1p/n, urx2p/n) v tx-diff-pp transmitter dynamic differential voltage swing range. 1600 mv pp v tx-rcv-detect amount of voltage change allowed during receiver detection 600 mv v tx-cm-idle-delta transmitter idle common-mode voltage change while in u2/u3 and not actively transmitting lfps ? 600 600 mv v tx-dc-cm common-mode voltage bias in the transmitter (dc) 1.75 v v tx-cm-ac-pp-active tx ac common-mode voltage active max mismatch from txp + txn for both time and amplitude 100 mv pp v tx-idle-diff-ac-pp ac electrical idle differential peak-to- peak output voltage at package pins 0 10 mv v tx-idle-diff-dc dc electrical idle differential output voltage at package pins after low pass filter to remove ac component 0 14 mv v tx-cm-dc-active-idle- delta absolute dc common-mode voltage between u1 and u0 at package pin 200 mv r tx-diff differential impedance of the driver 75 120 c ac-coupling ac coupling capacitor 75 265 nf r tx-cm common-mode impedance of the driver measured with respect to ac ground over 0 ? 500 mv 18 30
8 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated ac electrical characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit i tx-short tx short circuit current txp/n shorted to gnd 67 ma rl tx-diff differential return loss 50 mhz ? 1.25 ghz at 90 ? 16 db 2.5 ghz at 90 ? 13 db rl tx-cm common-mode return loss 50 mhz ? 2.5 ghz at 90 ? 11 db ac characteristics crosstalk differential crosstalk between any signal pairs at 4.05 ghz ? 30 db g lf low frequency voltage gain at 10 mhz, 200 mv pp < v id < 2000 mv pp ; 0-db low-frequency gain setting ? 1 0 1 db cp 1db-lf low frequency 1-db compression point at 10 mhz, 200 mv pp < v id < 2000 mv pp ; vod linearity setting = 1100mv pp 1100 mv pp cp 1db-hf high frequency 1-db compression point at 4.05 ghz, 200 mv pp < v id < 2000 mv pp ; vod linearity setting = 1100mv pp 1200 mv pp f lf low frequency cutoff 200 mv pp < v id < 2000 mv pp 25 50 khz dj tx output deterministic jitter 200 mv pp < v id < 2000 mv pp , prbs7, 5 gbps 0.05 uipp 200 mv pp < v id < 2000 mv pp , prbs7, 8.1 gbps 0.08 uipp tj tx output total jitter 200 mv pp < v id < 2000 mv pp , prbs7, 5 gbps 0.08 uipp 200 mv pp < v id < 2000 mv pp , prbs7, 8.1 gbps 0.135 uipp displayport receiver utx1p/n, utx2p/n, urx1p/n, urx2p/n v id_pp peak-to-peak input differential dynamic voltage range 2000 mv pp v ic input common mode voltage 0 v c ac ac coupling capacitance 75 200 nf eq dp receiver equalizer at maximum setting deq[1:0],ueq[1:0] at 4.05 ghz 9.5 db d r data rate hbr3 8.1 gbps r ti input termination resistance 80 100 120 displayport transmitter dtx1p/n, dtx2p/n, drx1p/n, drx2p/n v tx-diffpp vod dynamic range 1500 mv i tx-short tx short circuit current txp/n shorted to gnd 67 ma v tx(dc-cm) common-mode voltage bias in the transmitter (dc) 1.75 v auxp/n and sbu1/2 r on output on resistance v cc = 3.3 v; v i = 0 to 0.4 v for auxp; v i = 2.7 v to 3.6 v for auxn 5 10 r on on resistance mismatch within pair v cc = 3.3 v; v i = 0 to 0.4v for auxp; v i = 2.7v to 3.6v for auxn 1 r on_flat on resistance flatness (r on max ? r on min) measured at identical v cc and temperature v cc = 3.3 v; v i = 0 to 0.4v for auxp; v i = 2.7v to 3.6 v for auxn 2 v auxp_dc_cm aux channel dc common mode voltage for auxp and sbu1. v cc = 3.3 v 0 0.4 v v auxn_dc_cm aux channel dc common mode voltage for auxn and sbu2 v cc = 3.3 v 2.7 3.6 v c aux_on on-state capacitance v cc = 3.3v; ctl1 = 1; v i = 0v or 3.3v 4 7 pf c aux_off off-state capacitance v cc = 3.3v; ctl1 = 0; v i = 0v or 3.3v 3 6 pf
9 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.8 timing requirements min nom max unit usb gen 2 t idleentry delay from u0 to electrical idle see figure 4 10 ns t idelexit_u1 u1 exist time: break in electrical idle to the transmission of lfps see figure 4 6 ns t idleexit_u2u3 u2/u3 exit time: break in electrical idle to transmission of lfps 10 s t rxdet_intvl rx detect interval while in disconnect 12 ms t idleexit_disc disconnect exit time 15 ms t exit_shtdn shutdown exit time 1 ms t diff_dly differential propagation delay see figure 3 300 ps t r, t f output rise/fall time (see figure 5 ) 20%-80% of differential voltage measured 1 inch from the output pin 40 ps t rf_mm output rise/fall time mismatch 20%-80% of differential voltage measured 1 inch from the output pin 2.6 ps 6.9 switching characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit auxp/n and sbu1/2 t aux_pd switch propagation delay 400 ps t aux_sw_off switching time ctl1 to switch off. not including t ctl1_debounce . 500 ns t aux_sw_on switching time ctl1 to switch on 500 ns t aux_intra intra-pair output skew 100 ps usb3.1 and displayport mode transition requirement gpio mode t gp_usb_4dp min overlap of ctl1 and ctl1 when transitioning from usb 3.1 only mode to 4-lane displayport mode or vice versa. 4 s ctl1 and hpdin t ctl1_debounce ctl1 and hpdin debounce time when transitioning from h to l 3 10 ms i 2 c (refer to figure 1 ) f scl i 2 c clock frequency 1 mhz t buf bus free time between start and stop conditions 0.5 s t hdsta hold time after repeated start condition. after this period, the first clock pulse is generated 0.26 s t low low period of the i 2 c clock 0.5 s t high high period of the i 2 c clock 0.26 s t susta setup time for a repeated start condition 0.26 s t hddat data hold time 0 s t sudat data setup time 50 ns t r rise time of both sda and scl signals 120 ns t f fall time of both sda and scl signals 20 (v i2c /5.5 v) 120 ns t susto setup time for stop condition 0.26 s c b capacitive load for each bus line 100 pf
10 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 1. i2c timing diagram definitions figure 2. usb3.1 to 4-lane displayport in gpio mode figure 3. propagation delay in out t diff_dly t diff_dly ctl0 pin ctl1 pin 4us (min) t buf t hdsta t r t low t hddat t high t f t sudat t susta t hdsta t susto p s s p sda scl 30% 70% 30% 70%
11 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 4. electrical idle mode exit and entry delay figure 5. output rise and fall times figure 6. aux and sbu switch on and off timing diagram ctl1 v out 50% 90% 50% 10% t aux_sw_on t aux_sw_off + t ctl1_debounce t r t f 20% 80% t idleexit t idleentry in+ in- vcm out+ out- vcm v rx-lfps-det-diff-pp
12 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.10 typical characteristics figure 7. input return loss performance of the downstream ports figure 8. output return loss performance of the downstream ports figure 9. input return loss performance of the upstream ports figure 10. output return loss performance of the upstream ports 2.5 ghz figure 11. downstream-to-upstream linearity performance at 2.5 ghz 4.05 ghz figure 12. downstream-to-upstream linearity performance at 4.05 ghz differential input voltage (mvpp) differential output voltage (mvpp) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 d010 eq 0 eq 2 eq 4 eq 6 eq 8 eq 10 eq 12 eq 15 differential input voltage (mvpp) differential output voltage (mvpp) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 d008 eq 0 eq 2 eq 4 eq 6 eq 8 eq 10 eq 12 eq 15 frequency (ghz) sdd11 (db) 0 5 10 15 20 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 d003 frequency (ghz) sdd22 (db) 0 5 10 15 20 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 d004 frequency (ghz) sdd11 (db) 0 5 10 15 20 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 d001 frequency (ghz) sdd22 (db) 0 5 10 15 20 -35 -30 -25 -20 -15 -10 -5 0 d002
13 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) 100 mhz figure 13. downstream-to-upstream linearity performance at 100 mhz 2.5 ghz figure 14. upstream-to-downstream linearity performance at 2.5 ghz 4.05 ghz figure 15. upstream-to-downstream linearity performance at 4.05 ghz 100 mhz figure 16. upstream-to-downstream linearity performance at 100 mhz source data rate: 5 gbps swing: 1 vpp data pattern: prbs7 channel upstream-to-downstream, 12 in 6 mil input pcb channel settings eq setting: 7 dc gain setting: 0 db linear range setting: 1100 mvpp figure 17. output eye-pattern performance at 5 gbps source data rate: 8.1 gbps swing: 1 vpp data pattern: prbs7 channel upstream-to-downstream, 12 in 6 mil input pcb channel settings eq setting: 7 dc gain setting: 0 db linear range setting: 1100 mvpp figure 18. output eye-pattern performance at 8.1 gbps y axis title (unit) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 d011 eq 0 eq 2 eq 4 eq 6 eq 8 eq 10 eq 12 eq 15 differential input voltage (mvpp) differential output voltage (mvpp) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 d012 eq 0 differential input voltage (mvpp) differential output voltage (mvpp) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 d009 eq 0 differential input voltage (mvpp) differential output voltage (mvpp) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 d010 eq 0 eq 2 eq 4 eq 6 eq 8 eq 10 eq 12 eq 15
14 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) figure 19. upstream-to-downstream eq settings curves figure 20. downstream-to-upstream eq settings curves frequency (ghz) sdd21 (db) 0.01 0.1 1 10 2020 -10 -5 0 5 10 15 d006 eq0 eq1 eq2 eq3 eq4 eq5 eq6 eq7 eq8 eq9 eq10 eq11 eq12 eq13 eq14 eq15 frequency (ghz) sdd21 (db) 0.01 0.1 1 10 2020 -10 -5 0 5 10 15 d005 eq0 eq1 eq2 eq3 eq4 eq5 eq6 eq7 eq8 eq9 eq10 eq11 eq12 eq13 eq14 eq15
15 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7 detailed description 7.1 overview the tusb544 is a usb type-c alt mode redriver switch supporting data rates up to 8.1 gbps. this device implements 5th generation usb redriver technology. the device is utilized for configurations c, d, e, and f from the vesa displayport alt mode on usb type-c standard. it can also be configured to support custom usb type-c alternate modes. the tusb544 provides several levels of receive equalization to compensate for cable and board trace loss due to inter-symbol interference (isi) when usb 3.1 gen1 or displayport (or other alt modes) signals travel across a pcb or cable. this device requires a 3.3v power supply. it comes for both commercial temperature range and industrial temperature range operation. for host (source) or device (sink) applications the tusb544 enables the system to pass both transmitter compliance and receiver jitter tolerance tests for usb 3.1 gen 1 and displayport version 1.4 hbr3. the re-driver recovers incoming data by applying equalization that compensates for channel loss, and drives out signals with a high differential voltage. each channel has a receiver equalizer with selectable gain settings. equalization control for upstream and downstream facing ports can be set using ueq[1:0], and deq[1:0] pins respectively or through the i 2 c interface. moreover, the cfg[1:0] or the equivalent i 2 c registers provide the ability to control the eq dc gain and the voltage linearity range for all the channels (refer to table 8 ). this flexible control makes it easy to set up the device to pass various standard compliance requirements. the tusb544 advanced state machine makes it transparent to hosts and devices. after power up, the tusb544. periodically performs receiver detection on the tx pairs. if it detects a usb 3.1 gen1 receiver, the rx termination is enabled, and the tusb544 is ready to re-drive. the tusb544 provides extremely flexible data path signal direction control using the ctl[1:0], flip, dir[1:0], and swap pins or through the i2c interface. refer to table 4 for detailed information on the input to output signal pin mapping. the device ultra-low-power architecture operates at a 3.3 v power supply and achieves enhanced performance. the automatic lfps de-emphasis control further enables the system to be usb 3.1 compliant.
16 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.2 functional block diagram i2c_en ueq1/a1 ueq0/a0 sbu2 sbu1 ctl0/sda flip/scl vcc auxp auxn deq[1:0] vio_sel m u x vreg fsm, control logic & registers drx[2:1]eq_sel ctl1 aux rx i2c slave dtx2p drx1p drx2p dtx2n drx1n drx2n dtx1p dtx1n utx2p urx1p urx2p urx2n utx1n driver eq term term drx2eq_sel term urx2eq_sel eq eq driver term detect driver eq term term dtx2eq_sel term utx2eq_sel eq eq driver term utx2n driver eq term term dtx1eq_sel term utx1eq_sel eq eq driver term detect utx1p driver eq term term drx1eq_sel term urx1eq_sel eq eq driver term detect urx1n detect cfg[1:0] swap slp_s0# detect detect detect detect dtx[2:1]eq_sel urx[2:1]eq_sel utx[2:1]eq_sel dir[1:0] channel 0 channel 0 channel 1 channel 1 channel 2 channel 2 channel 3 channel 3 copyright ? 2017, texas instruments incorporated
17 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3 feature description 7.3.1 usb 3.1 the tusb544 supports usb 3.1 data rates up to 5 gbps. the tusb544 supports all the usb defined power states (u0, u1, u2, and u3). because the tusb544 is a linear redriver, it can ? t decode usb3.1 physical layer traffic. the tusb544 monitors the actual physical layer conditions like receiver termination, electrical idle, lfps, and superspeed signaling rate to determine the usb power state of the usb3.1 interface. the tusb544 features an intelligent low frequency periodic signaling (lfps) detector. the lfps detector automatically senses the low frequency signals and disables receiver equalization functionality. when not receiving lfps, the tusb544 will enable receiver equalization based on the ueq[1:0] and deq[1:0] pins or values programmed into ueq[3:0]_sel, and deq[3:0]_sel registers. 7.3.2 displayport the tusb544 supports up to 4 displayport lanes at data rates up to 8.1gbps (hbr3). the tusb544, when configured in displayport mode, monitors the native aux traffic as it traverses between displayport source and displayport sink. for the purposes of reducing power, the tusb544 will manage the number of active displayport lanes based on the content of the aux transactions. the tusb544 snoops native aux writes to displayport sink ? s dpcd registers 0x00101 (lane_count_set) and 0x00600 (set_power_state). tusb544 will disable/enable lanes based on value written to lane_count_set. the tusb544 will disable all lanes when set_power_state is in the d3. otherwise active lanes will be based on value of lane_count_set. displayport aux snooping is enabled by default but can be disabled by changing the aux_snoop_disable register. once aux snoop is disabled, management of tusb544 ? s displayport lanes are controlled through various configuration registers. 7.3.3 4-level inputs the tusb544 has (i2c_en, ueq[1:0], deq[1:0], cfg[1:0], and a[1:0]) 4-level inputs pins that are used to control the equalization gain, voltage linearity range, and place tusb544 into different modes of operation. these 4-level inputs utilize a resistor divider to help set the 4 valid levels and provide a wider range of control settings. there is an internal 30 k ? pull-up and a 94k ? pull-down. these resistors, together with the external resistor connection combine to achieve the desired voltage level. table 1. 4-level control pin settings level settings 0 option 1: tie 1 k ? 5% to gnd. option 2: tie directly to gnd. r tie 20 k ? 5% to gnd. f float (leave pin open) 1 option 1: tie 1 k ? 5%to v cc . option 2: tie directly to v cc . note all four-level inputs are latched on rising edge of internal reset. after t cfg_hd , the internal pull-up and pull-down resistors will be isolated in order to save power. 7.3.4 receiver linear equalization the purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in the system. the receiver overcomes these losses by attenuating the low frequency components of the signals with respect to the high frequency components. the proper gain setting should be selected to match the channel insertion loss. two 4-level input pins enable up to 16 possible equalization settings. the upstream path, and the downstream path each have their own two 4-level inputs for equalization settings; ueq[1:0] and deq[1:0] respectively. the tusb544 also provides the flexibility of adjusting equalization settings through i2c registers urx[2:1]eq_sel, utx[2:1]eq_sel, drx[2:1]eq_sel, and dtx[2:1]eq_sel for each individual channel and for each direction (upstream or downstream) .
18 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.4 device functional modes 7.4.1 device configuration in gpio mode the tusb544 is in gpio configuration when i2c_en = ? 0 ? . the tusb544 supports operational combinations with usb and two different type-c alternate modes.. one combination includes usb and alternate mode displayport, and the other combination includes usb and custom alternate mode. for each operational combination the data path directions can be further set using the dir[1:0] pins or through i2c to enable the device to operate in the source or sink sides. please refer to table 2 for all the configuration of all the operational modes. when the device is set to operate in a usb and alternate mode displayport the following configurations can be further set: usb3.1 only, 2 displayport lanes + usb3.1, or 4 displayport lanes (no usb3.1). the ctl1 pin controls whether displayport is enabled. the combination of ctl1 and ctl0 selects between usb3.1 only, 2 lanes of displayport, or 4-lanes of displayport as detailed in table 2 . the auxp/n to sbu1/2 mapping is controlled based on table 3 .. when the device is set to operate in a usb and custom alternate mode the following configurations can be further set: usb3.1 only, 2 channels of custom alternate mode + usb3.1, or 4 channels of custom alternate mode (no usb3.1). the ctl1 pin controls whether custom alternate mode is enabled. the combination of ctl1 and ctl0 selects between usb3.1 only, 2 channels of custom alternate mode, or 4 channels of custom alternate mode as detailed in table 2 . the auxp/n to sbu1/2 mapping is controlled based on table 3 . further data path direction control can be achieved using the swap pin. when set high, the swap pin reverses the data path direction on all the channels and swaps the equalization settings of the upstream and downstream facing input ports. this pin may be found useful in active cable application with tusb544 installed on only one end. the swap pin can be set based on which cable end is plugged to the source or sink side receptacle after power-up (vcc from 0 v to 3.3 v), the tusb544 will default to usb3.1 mode. the usb pd controller, upon detecting no device attached to type-c port or usb3.1 operation not required by attached device, must take tusb544 out of usb3.1 mode by transitioning the ctl0 pin from l to h and back to l. table 2. gpio configuration control dir1 pin dir0 pin ctl1 pin ctl0 pin flip pin tusb544 configuration vesa displayport alt mode dfp_d configuration usb + displayport alternate mode (source side) l l l l l power down/cable mode ? l l l l h power down/cable mode ? l l l h l one port usb 3.1 - no flip ? l l l h h one port usb 3.1 ? with flip ? l l h l l 4 lane dp - no flip c and e l l h l h 4 lane dp ? with flip c and e l l h h l one port usb 3.1 + 2 lane dp- no flip d and f l l h h h one port usb 3.1 + 2 lane dp ? with flip d and f usb + displayport alternate mode (sink side) l h l l l power down/cable mode ? l h l l h power down/cable mode ? l h l h l one port usb 3.1 - no flip ? l h l h h one port usb 3.1 ? with flip ? l h h l l 4 lane dp - no flip c and e l h h l h 4 lane dp ? with flip c and e l h h h l one port usb 3.1 + 2 lane dp- no flip d and f l h h h h one port usb 3.1 + 2 lane dp ? with flip d and f
19 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) table 2. gpio configuration control (continued) dir1 pin dir0 pin ctl1 pin ctl0 pin flip pin tusb544 configuration vesa displayport alt mode dfp_d configuration usb + custom alternate mode (source side) h l l l l power down/cable mode ? h l l l h power down/cable mode ? h l l h l one port usb 3.1 - no flip ? h l l h h one port usb 3.1 ? with flip ? h l h l l 4 channel custom alt mode - no flip ? h l h l h 4 channel custom alt mode ? with flip ? h l h h l one port usb 3.1 + 2 channel custom alt mode- no flip ? h l h h h one port usb 3.1 + 2 channel custom alt mode ? with flip ? usb + custom alternate mode (sink side) h h l l l power down/cable mode - h h l l h power down/cable mode - h h l h l one port usb 3.1 - no flip - h h l h h one port usb 3.1 ? with flip - h h h l l 4 channel custom alt mode - no flip - h h h l h 4 channel custom alt mode ? with flip - h h h h l one port usb 3.1 + 2 channel custom alt mode- no flip - h h h h h one port usb 3.1 + 2 channel custom alt mode ? with flip - table 3. gpio auxp/n to sbu1/2 mapping ctl1 pin flip pin mapping h l auxp - > sbu1 auxn - > sbu2 h h auxp - > sbu2 auxn - > sbu1 l > 2ms x open
20 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated details the tusb544 mux routing. this table is valid for both i 2 c and gpio. table 4. input to output mapping from to dir1 pin dir0 pin ctl1 pin ctl0 pin flip pin input pin output pin usb + displayport alternate mode (source side) l l l l l na na l l l l h na na l l l h l drx1p urx1p (ssrxp) drx1n urx1n (ssrxn) utx1p (sstxp) dtx1p utx1n (sstxn) dtx1n l l l h h drx2p urx2p (ssrxp) drx2n urx2n (ssrxn) utx2p (sstxp) dtx2p utx2n (sstxn) dtx2n l l h l l urx2p (dp0p) drx2p urx2n (dp0n) drx2n utx2p (dp1p) dtx2p utx2n (dp1n) dtx2n utx1p (dp2p) dtx1p utx1n (dp2n) dtx1n urx1p (dp3p) drx1p urx1n (dp3n) drx1n l l h l h urx1p (dp0p) drx1p urx1n (dp0n) drx1n utx1p (dp1p) dtx1p utx1n (dp1n) dtx1n utx2p (dp2p) dtx2p utx2n (dp2n) dtx2n urx2p (dp3p) drx2p urx2n (dp3n) drx2n l l h h l drx1p urx1p (ssrxp) drx1n urx1n (ssrxn) utx1p (sstxp) dtx1p utx1n (sstxn) dtx1n urx2p (dp0p) drx2p urx2n (dp0n) drx2n utx2p (dp1p) dtx2p utx2n (dp1n) dtx2n l l h h h drx2p urx2p (ssrxp) drx2n urx2n (ssrxn) utx2p (sstxp) dtx2p utx2n (sstxn) dtx2n urx1p (dp0p) drx1p urx1n (dp0n) drx1n utx1p (dp1p) dtx1p utx1n (dp1n) dtx1n usb + displayport alternate mode (sink side)
21 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated table 4. input to output mapping (continued) from to dir1 pin dir0 pin ctl1 pin ctl0 pin flip pin input pin output pin l h l l l na na l h l l h na na l h l h l utx2p dtx2p (ssrxp) utx2n dtx2n (ssrxn) drx2p (sstxp) urx2p drx2n (sstxn) urx2n l h l h h utx1p dtx1p (ssrxp) utx1n dtx1n (ssrxn) drx1p (sstxp) urx1p drx1n (sstxn) urx1n l h h l l urx2p drx2p (dp3p) urx2n drx2n (dp3n) utx2p dtx2p (dp2p) utx2n dtx2n (dp2n) utx1p dtx1p (dp1p) utx1n dtx1n (dp1n) urx1p drx1p (dp0p) l h h l h urx1n drx1n (dp1n) urx1p drx1p (dp3p) urx1n drx1n (dp3n) utx1p dtx1p (dp2p) utx1n dtx1n (dp2n) utx2p dtx2p (dp1p) utx2n dtx2n (dp1n) urx2p drx2p (dp0p) urx2n drx2n (dp0n) l h h h l drx2p (ssrxp) urx2p drx2n (ssrxn) urx2n utx2p dtx2p (sstxp) utx2n dtx2n (sstxn) urx1p drx1p (dp0p) urx1n drx1n (dp0n) utx1p dtx1p (dp1p) utx1n dtx1n (dp1n) l h h h h drx1p (ssrxp) urx1p drx1n (ssrxn) urx1n utx1p dtx1p (sstxp) utx1n dtx1n (sstxn) urx2p drx2p (dp0p) urx2n drx2n (dp0n) utx2p dtx2p (dp1p) utx2n dtx2n (dp1n) usb + custom alternate mode (source side) h l l l l na na h l l l h na na
22 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated table 4. input to output mapping (continued) from to dir1 pin dir0 pin ctl1 pin ctl0 pin flip pin input pin output pin h l l h l drx1p urx1p (ssrxp) drx1n urx1n (ssrxn) utx1p (sstxp) dtx1p utx1n (sstxn) dtx1n h l l h h drx2p urx2p (ssrxp) drx2n urx2n (ssrxn) utx2p (sstxp) dtx2p utx2n (sstxn) dtx2n h l h l l drx2p urx2p (ln1rxp) drx2n urx2n (ln1rxn) utx2p (ln1txp) dtx2p utx2n (ln1txn) dtx2n utx1p (ln0txp) dtx1p utx1n (ln0txn) dtx1n drx1p urx1p (ln0rxp) drx1n urx1n (ln0rxn) h l h l h drx1p urx1p (ln1rxp) drx1n urx1n (ln1rxn) utx1p (ln1txp) dtx1p utx1n (ln1txn) dtx1n utx2p (ln0txp) dtx2p utx2n (ln0txn) dtx2n h l h h l drx2p urx2p (ln0rxp) drx2n urx2n (ln0rxn) drx1p urx1p (ssrxp) drx1n urx1n (ssrxn) utx1p (sstxp) dtx1p utx1n (sstxn) dtx1n utx2p (ln0txp) dtx2p utx2n (ln0txn) dtx2n drx2p urx2p (ln0rxp) drx2n urx2n (ln0rxn) h l h h h drx2p urx2p (ssrxp) drx2n urx2n (ssrxn) utx2p (sstxp) dtx2p utx2n (sstxn) dtx2n utx1p (ln0txp) dtx1p utx1n (ln0txn) dtx1n drx1p urx1p (ln0rxp) drx1n urx1n (ln0rxn) usb + custom alternate mode (sink side) h h l l l na na h h l l h na na
23 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated table 4. input to output mapping (continued) from to dir1 pin dir0 pin ctl1 pin ctl0 pin flip pin input pin output pin h h l h l utx2p dtx2p (ssrxp) utx2n dtx2n (ssrxn) drx2p (sstxp) urx2p drx2n (sstxn) urx2n h h l h h utx1p dtx1p (ssrxp) utx1n dtx1n (ssrxn) drx1p (sstxp) urx1p drx1n (sstxn) urx1n h h h l l drx2p urx2p (ln1txp) drx2n urx2n (ln1txn) utx2p (ln1rxp) dtx2p utx2n (ln1rxn) dtx2n utx1p (ln0rxp) dtx1p utx1n (ln0rxn) dtx1n drx1p urx1p (ln0rxp) drx1n urx1n (ln0rxn) h h h l h drx2p urx2p (ln0rxp) drx2n urx2n (ln0rxn) utx2p (ln0rxp) dtx2p utx2n (ln0rxn) dtx2n utx1p (ln0rxp) dtx1p utx1n (ln0rxn) dtx1n drx1p urx1p (ln0txp) drx1n urx1n (ln0txn) h h h h l utx2p dtx2p (ssrxp) utx2n dtx2n (ssrxn) drx2p (sstxp) urx2p drx2n (sstxn) urx2n utx1p dtx1p (ln0rxp) utx1n dtx1n(ln0rxn) drx1p (ln0txp) urx1p drx1n (ln0txn) urx1n h h h h h utx1p dtx1p (ssrxp) utx1n dtx1n (ssrxn) drx1p (sstxp) urx1p drx1n (sstxn) urx1n drx2p urx2p (ln0txp) drx2n urx2n (ln0txn) utx2p (ln0rxp) dtx2p utx2n (ln0rxn) dtx2n 7.4.2 device configuration in i2c mode the tusb544 is in i2c mode when i2c_en is not equal to ? 0 ? . the same configurations defined in gpio mode are also available in i2c mode. the tusb544 ? s usb3.1, displayport, and custom alternate mode configuration is controlled based on table 5 . the auxp/n to sbu1/2 mapping control is based on table 5 .
24 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated table 5. i2c configuration control registers tusb544 configuration vesa displayport alt mode dfp_d configuration dirsel1 dirsel0 ctlsel1 ctlsel0 flipsel usb + displayport alternate mode (source side) l l l l l power down ? l l l l h power down ? l l l h l one port usb 3.1 - no flip ? l l l h h one port usb 3.1 ? with flip ? l l h l l 4 lane dp - no flip c and e l l h l h 4 lane dp ? with flip c and e l l h h l one port usb 3.1 + 2 lane dp- no flip d and f l l h h h one port usb 3.1 + 2 lane dp ? with flip d and f usb + displayport alternate mode (sink side) l h l l l power down ? l h l l h power down ? l h l h l one port usb 3.1 - no flip ? l h l h h one port usb 3.1 ? with flip ? l h h l l 4 lane dp - no flip c and e l h h l h 4 lane dp ? with flip c and e l h h h l one port usb 3.1 + 2 lane dp- no flip d and f l h h h h one port usb 3.1 + 2 lane dp ? with flip d and f usb + custom alternate mode (source side) h l l l l power down ? h l l l h power down ? h l l h l one port usb 3.1 - no flip ? h l l h h one port usb 3.1 ? with flip ? h l h l l 4 channel custom alt mode - no flip ? h l h l h 4 channel custom alt mode ? with flip ? h l h h l one port usb 3.1 + 2 channel custom alt mode- no flip ? h l h h h one port usb 3.1 + 2 channel custom alt mode ? with flip ? usb + custom alternate mode (sink side) h h l l l power down ? h h l l h power down ? h h l h l one port usb 3.1 - no flip ? h h l h h one port usb 3.1 ? with flip ? h h h l l 4 channel custom alt mode - no flip ? h h h l h 4 channel custom alt mode ? with flip ? h h h h l one port usb 3.1 + 2 channel custom alt mode- no flip ?
25 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated table 5. i2c configuration control (continued) registers tusb544 configuration vesa displayport alt mode dfp_d configuration dirsel1 dirsel0 ctlsel1 ctlsel0 flipsel h h h h h one port usb 3.1 + 2 channel custom alt mode ? with flip ? table 6. i2c auxp/n to sbu1/2 mapping registers aux_sbu_ovr ctlsel1 flipsel mapping 00 h l auxp - > sbu1 auxn - > sbu2 00 h h auxp - > sbu2 auxn - > sbu1 00 l x open 01 x x auxp - > sbu1 auxn - > sbu2 10 x x auxp - > sbu2 auxn - > sbu1 11 x x open 7.4.3 displayport mode the tusb544 supports up to four displayport lanes at datarates up to 8.1gbps. tusb544 can be enabled for displayport through gpio control or through i2c register control. when i2c_en is ? 0 ? , displayport is controlled based on table 2 . when not in gpio mode, enable of displayport functionality is controlled through i 2 c registers. 7.4.4 custom alternate mode the tusb544 supports up to two lanes (or 4 channels) of custom alternate mode at datarates up to 8.1gbps. tusb544 can be enabled for custom alternate mode through gpio control or through i 2 c register control. when i2c_en is ? 0 ? , custom alternate mode is controlled based on table 2 . when not in gpio mode, enable of custom alternate mode functionality is controlled through i2c registers. in i2c mode, the operation of this mode requires setting up aux_snoop_disable register 0x13 bit 7 to 0. 7.4.5 cable mode cable mode is designed for applications within a cable, where the pd controller may not be able to provide usb/dp mode information. it is therefore necessary for the device to recognize the correct mode and automatically update modes on-the-fly. in gpio mode, cable mode is set by keeping the ctl0 and ctl1 pins low at all times. in i2c mode, cable mode is set by writing a 1 to register 0x0a.6. it is expected that the pd controller can provide hpdin. in cable mode, this pin is synonymous with ctl1 in normal mode. when high, dp mode will be active (with or without usb), and when low, usb-only will be active. aux snooping is active by default in cable mode. through aux snooping the device can be set in either 1 lane dp, 2 lane dp or 4 lane dp if aux snooping is disabled in cable mode, 2-lane dp mode is activated when hpdin is set high. 4-lane dp mode is ultimately set if usb mode is not detected. 7.4.6 linear eq configuration tusb544 receiver lanes have controls for receiver equalization for upstream and downstream facing ports. the receiver equalization gain value can be controlled either through i2c registers or through gpios. table 7 details the gain value for each available combination when tusb544 is in gpio mode. these same options are also available per channel and for upstream and downstream facing ports in i2c mode by updating registers urx[2:1]eq_sel, utx[2:1]eq_sel, drx[2:1]eq_sel, and dtx[2:1]eq_sel.
26 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated table 7. tusb544 receiver equalization gpio control downstream facing ports upstream facing port deq1 pin level deq0 pin level eq gain 2.5ghz (db) eq gain 4.05ghz (db) ueq1 pin level ueq0 pin level eq gain 2.5ghz (db) eq gain 4.05ghz (db) 0 0 -1.0 -1.4 0 0 -2.2 -3.3 0 r 0.1 0.4 0 r -1.1 -1.5 0 f 1.0 1.7 0 f -0.2 0.0 0 1 2.1 3.2 0 1 0.9 1.4 r 0 2.9 4.1 r 0 1.8 2.4 r r 3.8 5.2 r r 2.7 3.5 r f 4.6 6.1 r f 3.4 4.3 r 1 5.4 6.9 r 1 4.3 5.2 f 0 6.1 7.7 f 0 5.0 6.0 f r 6.8 8.3 f r 5.7 6.6 f f 7.3 8.8 f f 6.2 7.2 f 1 7.9 9.4 f 1 6.8 7.7 1 0 8.4 9.8 1 0 7.3 8.1 1 r 8.9 10.3 1 r 7.8 8.6 1 f 9.3 10.6 1 f 8.2 9.0 1 1 9.8 11.0 1 1 8.7 9.4 7.4.7 adjustable vod linear range and dc gain the cfg0 and cfg1 pins can be used to adjust the tusb544 differential output voltage (vod) swing linear range and receiver equalization dc gain for both downstream and upstream data path directions. table 8 details the available options. table 8. vod linear range and dc gain setting # cfg1 pin level cfg0 pin level downstream dc gain (db) upstream dc gain (db) downstream vod linear range (mvpp) upstream vod linear range (mvpp) 1 0 0 1 0 900 900 2 0 r 0 1 900 900 3 0 f 0 0 900 900 4 0 1 1 1 900 900 5 r 0 0 0 1100 1100 6 r r 1 0 1100 1100 7 r f 0 1 1100 1100 8 r 1 2 2 1100 1100 9 f 0 reserved reserved reserved reserved 10 f r reserved reserved reserved reserved 11 f f reserved reserved reserved reserved 12 f 1 reserved reserved reserved reserved 13 1 0 reserved reserved reserved reserved 14 1 r reserved reserved reserved reserved 15 1 f reserved reserved reserved reserved 16 1 1 reserved reserved reserved reserved
27 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.4.8 usb3.1 modes the tusb544 monitors the physical layer conditions like receiver termination, electrical idle, lfps, and superspeed signaling rate to determine the state of the usb3.1 interface. depending on the state of the usb 3.1 interface, the tusb544 can be in one of four primary modes of operation when usb 3.1 is enabled (ctl0 = h or ctlsel0 = 1b1): disconnect, u2/u3, u1, and u0. the disconnect mode is the state in which tusb544 has not detected far-end termination on both upstream facing port (ufp) or downstream facing port (dfp). the disconnect mode is the lowest power mode of each of the four modes. the tusb544 will remain in this mode until far-end receiver termination has been detected on both ufp and dfp. the tusb544 will immediately exit this mode and enter u0 once far-end termination is detected. once in u0 mode, the tusb544 will redrive all traffic received on ufp and dfp. u0 is the highest power mode of all usb3.1 modes. the tusb544 will remain in u0 mode until electrical idle occurs on both ufp and dfp. upon detecting electrical idle, the tusb544 will immediately transition to u1. the u1 mode is the intermediate mode between u0 mode and u2/u3 mode. in u1 mode, the tusb544 ? s ufp and dfp receiver termination will remain enabled. the ufp and dfp transmitter dc common mode is maintained. the power consumption in u1 will be similar to power consumption of u0. next to the disconnect mode, the u2 and u3 mode is next lowest power state. while in this mode, the tusb544 will periodically perform far-end receiver detection. anytime the far-end receiver termination is not detected on either ufp or dfp, the tusb544 will leave the u2 and u3 mode and transition to the disconnect mode. it will also monitor for a valid lfps. upon detection of a valid lfps, the tusb544 will immediately transition to the u0 mode. in u2 and u3 mode, the tusb544 ? s receiver terminations will remain enabled but the tx dc common mode voltage will not be maintained. when slp_s0# is asserted low it will disable receiver detect functionality. while slp_s0# is low and tusb544 is in u2 and u3, tusb544 will disable los and lfps detection circuitry and rx termination for both channels will remain enabled. this allows even lower tusb544 power consumption while in the u2 and u3 mode. once slp_s0# is asserted high, the tusb544 will again start performing far-end receiver detection as well as monitor lfps so it can know when to exit the u2 and u3 mode. when slp_s0# is asserted low and the tusb544 is in disconnect mode, the tusb544 will remain in disconnect mode and never perform far-end receiver detection. this allows even lower tusb544 power consumption while in the disconnect mode. once slp_s0# is asserted high, the tusb544 will again start performing far-end receiver detection so it can know when to exit the disconnect mode.
28 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.4.9 operation timing ? power up figure 21. power-up timing t d_pg v cc internal power good t cfg_su t cfg_hd disabled usb3.1-only flip = 0 if ((ctl[1:0] == 2'b00 | ctl[1:0] == 2'b01) & flip == 0 ) { usb3.1-only no flip; } elseif ((ctl[1:0] == 2'b00 | ctl[1:0] == 2'b01) & flip == 1 ) { usb3.1-only with flip; } elseif (ctl[1:0] == 2'b10 & flip == 0) { 4-lane dp no flip; } elseif (ctl[1:0] == 2'b10 & flip == 1) { 4-lane dp with flip; } elseif (ctl[1:0] == 2'b11 & flip == 0) { 2-lane dp usb3.1 no flip; }else { 2-lane dp usb3.1 with flip; }; ctl[1:0] pins flip pin cfg pins tusb544 in gpio mode disabled usb3.1-only flip = 0 tusb544 in i2c mode mode of operation determined by value of flipsel bit and ctlsel[1:0] bits at offset 0x0a. default is usb3.1-only no flip. t ctl_db v cc (min)
29 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) following pins comprise cfg pins: i2c_en, ueq[1:0], deq[1:0], cfg[1:0], dir[1:0],vio_sel, slp_s0#, and swap. (2) recommend cfg pins are stable when vcc is at min. table 9. power-up timing parameter min max unit t d_pg v cc (min) to internal power good asserted high 500 s t cfg_su cfg (1) pins setup (2) 350 ms t cfg_hd cfg (1) pins hold 10 s t ctl_db ctl[1:0] and flip pin debounce 16 ms t vcc_ramp vcc supply ramp requirement 100 ms 7.5 programming for further programmability, the tusb544 can be controlled using i2c. the scl and sda terminals are used for i2c clock and i2c data respectively. table 10. i2c slave address tusb544 i2c slave address ueq1/a1 pin level ueq0/a0 pin level bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (w/r) 0 0 1 0 0 0 1 0 0 0/1 0 r 1 0 0 0 1 0 1 0/1 0 f 1 0 0 0 1 1 0 0/1 0 1 1 0 0 0 1 1 1 0/1 r 0 0 1 0 0 0 0 0 0/1 r r 0 1 0 0 0 0 1 0/1 r f 0 1 0 0 0 1 0 0/1 r 1 0 1 0 0 0 1 1 0/1 f 0 0 0 1 0 0 0 0 0/1 f r 0 0 1 0 0 0 1 0/1 f f 0 0 1 0 0 1 0 0/1 f 1 0 0 1 0 0 1 1 0/1 1 0 0 0 0 1 1 0 0 0/1 1 r 0 0 0 1 1 0 1 0/1 1 f 0 0 0 1 1 1 0 0/1 1 1 0 0 0 1 1 1 1 0/1 7.5.1 the following procedure should be followed to write to tusb544 i 2 c registers: 1. the master initiates a write operation by generating a start condition (s), followed by the tusb544 7-bit address and a zero-value ? w/r ? bit to indicate a write cycle . 2. the tusb544 acknowledges the address cycle. 3. the master presents the sub-address (i 2 c register within tusb544) to be written, consisting of one byte of data, msb-first. 4. the tusb544 acknowledges the sub-address cycle. 5. the master presents the first byte of data to be written to the i 2 c register. 6. the tusb544 acknowledges the byte transfer. 7. the master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the tusb544. 8. the master terminates the write operation by generating a stop condition (p).
30 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.5.2 the following procedure should be followed to read the tusb544 i 2 c registers: 1. the master initiates a read operation by generating a start condition (s), followed by the tusb544 7-bit address and a one-value ? w/r ? bit to indicate a read cycle 2. the tusb544 acknowledges the address cycle. 3. the tusb544 transmit the contents of the memory registers msb-first starting at register 00h or last read sub-address+1. if a write to the t i2c register occurred prior to the read, then the tusb544 shall start at the sub-address specified in the write. 4. the tusb544 shall wait for either an acknowledge (ack) or a not-acknowledge (nack) from the master after each byte transfer; the i 2 c master acknowledges reception of each data byte transfer. 5. if an ack is received, the tusb544 transmits the next byte of data. 6. the master terminates the read operation by generating a stop condition (p). 7.5.3 the following procedure should be followed for setting a starting sub-address for i 2 c reads: 1. the master initiates a write operation by generating a start condition (s), followed by the tusb544 7-bit address and a zero-value ? w/r ? bit to indicate a write cycle. 2. the tusb544 acknowledges the address cycle. 3. the master presents the sub-address (i2c register within tusb544) to be written, consisting of one byte of data, msb-first. 4. the tusb544 acknowledges the sub-address cycle. 5. the master terminates the write operation by generating a stop condition (p). note if no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the i 2 c master terminates the read operation. if a i 2 c address write occurred prior to the read, then the reads start at the sub-address specified by the address write. 7.6 register maps 7.6.1 tusb544 registers table 11 lists the memory-mapped registers for the tusb544. all register offset addresses not listed in table 11 should be considered as reserved locations and the register contents should not be modified. table 11. tusb544 registers offset acronym register name section ah general_4 general registers 4 go bh general_5 general register 5 go ch general_6 general register 6 go 10h displayport_1 displayport control/status registers 1 go 11h displayport_2 displayport control/status registers 2 go 12h displayport__3 displayport control/status registers 3 go 13h displayport_4 displayport control/status registers 4 go 1bh displayport_5 displayport control/status registers 5 go 20h usb3.1_1 usb3.1 control/status registers 1 go 21h usb3.1_2 usb3.1 control/status registers 2 go 22h usb3.1_3 usb3.1 control/status registers 3 go 23h usb3.1_4 usb3.1 control/status registers 4 go
31 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated complex bit access types are encoded to fit into small table cells. table 12 shows the codes that are used for access types in this section. table 12. tusb544 access type codes access type code description read type r r read ru r read write type w w write wu w write reset or default value - n value after reset or the default value 7.6.1.1 general_4 register (offset = ah) [reset = 1h] general_4 is shown in figure 22 and described in table 13 . return to summary table . figure 22. general_4 register 7 6 5 4 3 2 1 0 reserved cable_mode swap_sel eq_overide hpdin_over ride flipsel ctlsel[1:0] r-0h 0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-1h table 13. general_4 register field descriptions bit field type reset description 7 reserved r 0h reserved 6 cable_mode 0h 0 ? normal mode of operation 1 ? cable mode of operation. dp lane activation is performed through aux snooping and hpdin status. if aux snooping is disabled, 2 dp lanes are activated by default. 4 dp lanes are activated if usb ss is not detected. 5 swap_sel r/w 0h setting of this field performs global direction swap on all the channels 0 ? channel directions and eq settings are in normal mode (default) 1 ? reverse all channel directions and eq settings for the input ports 4 eq_overide r/w 0h setting of this field will allow software to use eq settings from registers instead of value sample from pins. 0 ? eq settings based on sampled state of the eq pins. 1 ? eq settings based on programmed value of each of the eq registers 3 hpdin_override r/w 0h 0 ? hpd in based on state of hpd_in pin (default) 1 ? hpd_in high. 2 flipsel r/w 0h flipsel. refer to table 5 and table 6 for this field functionality. 1-0 ctlsel[1:0] r/w 1h 00 ? disabled. all rx and tx for usb3 and displayport are disabled. 01 ? usb3.1 only enabled. (default) 10 ? four displayport lanes enabled. 11 ? two displayport lanes and one usb3.1
32 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.2 general_5 register (offset = bh) [reset = 0h] general_5 is shown in figure 23 and described in table 14 . return to summary table . figure 23. general_5 register 7 6 5 4 3 2 1 0 reserved reserved ch_swap_sel r-0h r-0h r/w-0h table 14. general_5 register field descriptions bit field type reset description 7-6 reserved r 0h reserved 5-4 reserved r 0h reserved 3-0 ch_swap_sel r/w 0h setting of this field swaps direction (tx to rx and rx to tx) and eq settings of individual channels. channels are numbered 0 to 3 from top to bottom (see block diagram on figure 8.1). 0 ? channel direction and eq setting are in normal mode (default) 1 ? reverse channel direction and eq setting for the input port. for example, setting 0x0b[3:0] to 4b1100 swaps directions and eq settings only on channels 2 and 3 7.6.1.3 general_6 register (offset = ch) [reset = 0h] general_6 is shown in figure 24 and described in table 15 . return to summary table . figure 24. general_6 register 7 6 5 4 3 2 1 0 reserved vod_dcgain _override vod_dcgain_sel dir_sel[1:0] r-0h r/w-0h r/wu-0h r/w-0h table 15. general_6 register field descriptions bit field type reset description 7 reserved r 0h reserved 6 vod_dcgain_overrid e r/w 0h setting of this field will allow software to use vod linearity range and dc gain settings from registers instead of value sampled from pins. 0 ? vod linearity range and dc gain settings based on sampled state of cfg[2:1] pins. 1 ? eq settings based on programmed value of each of the vod linearity range and dc gain registers 5-2 vod_dcgain_sel r/wu 0h field selects vod linearity range and dc gain for all the channels and in all directions. when vod_dcgain_override = 1 ? b0, this field reflects the sampled state of cfg[1:0] pins. when vod_dcgain_override = 1 ? b1, software can change the vod linearity range and dc gain for all the channels and in all directions based on value written to this field. refer to table 8 8. each cfg is a 2-bit value. the register-to-cfg1/0 mapping is: [5:2] = {cfg1[1:0], cfg0[1:0]} where cfgx[1:0] mapping is: 00 = 0 01 = r 10 = f 11 = 1 1-0 dir_sel[1:0] r/w 0h dir_sel[1:0]. sets operation mode 00 ? usb + dp alt mode (source) (default) 01 ? usb + dp alt mode (sink) 10 ? usb + custom alt mode (source) 11 ? usb + custom alt mode (sink)
33 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.4 displayport_1 register (offset = 10h) [reset = 0h] displayport is shown in figure 25 and described in table 16 . return to summary table . figure 25. displayport register 7 6 5 4 3 2 1 0 utx2eq_sel urx2eq_sel r/wu-0h r/wu-0h table 16. displayport register field descriptions bit field type reset description 7-4 utx2eq_sel rwu 0h field selects between 0 to 9.4 db of eq for utx2p/n pins. when eq_override = 1 ? b0, this field reflects the sampled state of ueq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for utx2p/n pins based on value written to this field. 3-0 urx2eq_sel rwu 0h field selects between 0 to 9.4 db of eq for urx2p/n pins. when eq_override = 1 ? b0, this field reflects the sampled state of ueq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for urx2p/n pins based on value written to this field. 7.6.1.5 displayport_2 register (offset = 11h) [reset = 0h] displayport_2 is shown in figure 26 and described in table 17 . return to summary table . figure 26. displayport_2 register 7 6 5 4 3 2 1 0 utx1eq_sel urx1eq_sel r/wu-0h r/wu-0h table 17. displayport_2 register field descriptions bit field type reset description 7-4 utx1eq_sel r/wu 0h field selects between 0 to 9.4 db of eq for utx1p/n pins. when eq_override = 1 ? b0, this field reflects the sampled state of ueq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for utx1p/n pins based on value written to this field. 3-0 urx1eq_sel r/wu 0h field selects between 0 to 9.4 db of eq for urx1p/n pins. when eq_override = 1 ? b0, this field reflects the sampled state of ueq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for urx1p/n pins based on value written to this field.
34 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.6 displayport__3 register (offset = 12h) [reset = 0h] displayport__3 is shown in figure 27 and described in table 18 . return to summary table . figure 27. displayport__3 register 7 6 5 4 3 2 1 0 reserved set_power_state lane_count_set r-0h ru-0h ru-0h table 18. displayport__3 register field descriptions bit field type reset description 7 reserved r 0h reserved 6-5 set_power_state ru 0h this field represents the snooped value of the aux write to dpcd address 0x00600. when aux_snoop_disable = 1 ? b0, the tusb544 will enable/disable dp lanes based on the snooped value. when aux_snoop_disable = 1 ? b1, then dp lane enable/disable are determined by state of dpx_disable registers, where x = 0, 1, 2, or 3. this field is reset to 2 ? b00 by hardware when ctlsel1 changes from a 1 ? b1 to a 1 ? b0. 4-0 lane_count_set ru 0h this field represents the snooped value of aux write to dpcd address 0x00101 register. when aux_snoop_disable = 1 ? b0, tusb544 will enable dp lanes specified by the snoop value. unused dp lanes will be disabled to save power. when aux_snoop_disable = 1 ? b1, then dp lanes enable/disable are determined by dpx_disable registers, where x = 0, 1, 2, or 3. this field is reset to 0x0 by hardware when ctlsel1 changes from a 1 ? b1 to a 1 ? b0.
35 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.7 displayport_4 register (offset = 13h) [reset = 0h] displayport_4 is shown in figure 28 and described in table 19 . return to summary table . figure 28. displayport_4 register 7 6 5 4 3 2 1 0 aux_snoop_ disable reserved aux_sbu_ovr dp3_disable dp2_disable dp1_disable dp0_disable r/w-0h r-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h table 19. displayport_4 register field descriptions bit field type reset description 7 aux_snoop_disable r/w 0h 0 ? aux snoop enabled. (default) 1 ? aux snoop disabled. 6 reserved r 0h reserved 5-4 aux_sbu_ovr r/w 0h this field overrides the auxp/n to sbu1/2 connect and disconnect based on ctl1 and flip. changing this field to 1 ? b1 will allow traffic to pass through aux to sbu regardless of the state of ctlsel1 and flipsel register. 00 ? aux to sbu connect/disconnect determined by ctlsel1 and flipsel (default) 01 ? auxp - > sbu1 and auxn - > sbu2 connection always enabled. 10 ? auxp - > sbu2 and auxn - > sbu1 connection always enabled. 1 1 = aux to sbu open. 3 dp3_disable r/w 0h when aux_snoop_disable = 1b1, this field can be used to enable or disable dp lane 3. when aux_snoop_disable = 1b0, changes to this field will have no effect on lane 3 functionality. 0 ? dp lane 3 enabled (default) 1 ? dp lane 3 disabled. 2 dp2_disable r/w 0h when aux_snoop_disable = 1 'b1, this field can be used to enable or disable dp lane 2. when aux_snoop_disable = 1b0, changes to this field will have no effect on lane 2 functionality. 0 ? dp lane 2 enabled (default) 1 ? dp lane 2 disabled. 1 dp1_disable r/w 0h when aux_snoop_disable = 1 ? b1, this field can be used to enable or disable dp lane 1. when aux_snoop_disable = 1 ? b0, changes to this field will have no effect on lane 1 functionality. 0 ? dp lane 1 enabled (default) 1 ? dp lane 1 disabled. 0 dp0_disable r/w 0h when aux_snoop_disable = 1 ? b1, this field can be used to enable or disable dp lane 0. when aux_snoop_disable = 1 ? b0, changes to this field will have no effect on lane 0 functionality. 0 ? dp lane 0 enabled (default) 1 ? dp lane 0 disabled.
36 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.8 displayport_5 register (offset = 1bh) [reset = 0h] displayport_5 is shown in figure 29 and described in table 20 . return to summary table . figure 29. displayport_5 register 7 6 5 4 3 2 1 0 i2c_rst dpcd_rst 0h 0h table 20. displayport_5 register field descriptions bit field type reset description 7-4 i2c_rst 0h resets i2c registers to default values. this field is self- clearing. 3-0 dpcd_rst 0h resets dpcd registers to default values. this field is self- clearing. 7.6.1.9 usb3.1_1 register (offset = 20h) [reset = 0h] usb3.1 is shown in figure 30 and described in table 21 . return to summary table . figure 30. usb3.1 register 7 6 5 4 3 2 1 0 dtx2eq_sel drx2eq_sel r/wu-0h r/wu-0h table 21. usb3.1 register field descriptions bit field type reset description 7-4 dtx2eq_sel r/wu 0h field selects between 0 to 11 db of eq for dtx2p/n pins. when eq_override = 1 ? b0, this field reflects the sampled state of deq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for dtx2p/n pins based on value written to this field. 3-0 drx2eq_sel r/wu 0h field selects between 0 to 11 db of eq for drx2p/n pins. when eq_override = 1 ? b0, this field reflects the sampled state of deq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for drx2p/n pins based on value written to this field.
37 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.10 usb3.1_2 register (offset = 21h) [reset = 0h] usb3.1_2 is shown in figure 31 and described in table 22 . return to summary table . figure 31. usb3.1_2 register 7 6 5 4 3 2 1 0 dtx1eq_sel drx1eq_sel r/w-0h r/wu-0h table 22. usb3.1_2 register field descriptions bit field type reset description 7-4 dtx1eq_sel r/w 0h field selects between 0 to 11 db of eq for dtx1p/n pins. when eq_override = 1 ? b0, this field reflects the sampled state of deq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for dtx1p/n pins based on value written to this field. 3-0 drx1eq_sel r/wu 0h field selects between 0 to 11 db of eq for drx1p/n pins. when eq_override = 1 ? b0, this field reflects the sampled state of deq[1:0] pins. when eq_override = 1 ? b1, software can change the eq setting for drx1p/n pins based on value written to this field. 7.6.1.11 usb3.1_3 register (offset = 22h) [reset = 0h] usb3.1_3 is shown in figure 32 and described in table 23 . return to summary table . figure 32. usb3.1_3 register 7 6 5 4 3 2 1 0 cm_active lfps_eq u2u3_lfps_d ebounce disable_u2u 3_rxdet dfp_rxdet_interval usb3_compliance_ctrl r/wu-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h table 23. usb3.1_3 register field descriptions bit field type reset description 7 cm_active r/wu 0h 0 - device not in usb 3.1 compliance mode. (default) 1 - device in usb 3.1 compliance mode 6 lfps_eq r/w 0h controls whether settings of eq based on urx[2:1]eq_sel, utx[2:1]eq_sel, drx[2:1]eq_sel, and dtx[2:1]eq_sel applies to received lfps signal. 0 - eq set to zero when receiving lfps (default) 1 - eq set by the related registers when receiving lfps. 5 u2u3_lfps_debounce r/w 0h 0 - no debounce of lfps before u2/u3 exit. (default) 1 - 200us debounce of lfps before u2/u3 exit. 4 disable_u2u3_rxdet r/w 0h 0 - rx.detect in u2/u3 enabled. (default) 1 - rx.detect in u2/u3 disabled. 3-2 dfp_rxdet_interval r/w 0h this field controls the rx.detect interval for the downstream facing port (tx1p/n and tx2p/n). 00 - 8 ms 01 - 12 ms (default) 10 - reserved 11 - reserved 1-0 usb3_compliance_ct rl r/w 0h 00 - fsm determined compliance mode. (default) 01 - compliance mode enabled in dfp direction (utx1/utx2 dtx1/dtx2) 10 - compliance mode enabled in ufp direction (drx1/drx2 urx1/urx2) 11 - compliance mode disabled.
38 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.6.1.12 usb3.1_4 register (offset = 23h) [reset = 0h] usb3.1_4 is shown in figure 33 and described in table 24 . return to summary table . figure 33. usb3.1_4 register 7 6 5 4 3 2 1 0 reserved cfg_los_hyst cfg_los_vth r-0h r/w-0h r/w-0h table 24. usb3.1_4 register field descriptions bit field type reset description 7-6 reserved r 0h reserved 5-3 cfg_los_hyst r/w 0h controls los hysteresis defined as 20 log (los de-assert threshold/los assert threshold). 000 - 0.15 db 001 - 0.85 db 010 - 1.45 db 011 - 2.00 db 100 - 2.70 db (default) 101 - 3.00 db 110 - 3.40 db 111 - 3.80 db 2-0 cfg_los_vth r/w 0h controls los assert threshold voltage 000 - 67 mv 001 - 72 mv 010 - 79 mv 011 - 85 mv (default) 100 - 91 mv 101 - 97 mv 110 - 105 mv 111 - 112 mv
39 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tusb544 is a linear redriver designed specifically to compensate for intersymbol interference (isi) jitter caused by signal attenuation through a passive medium like pcb traces and cables. because the tusb544 has four independent inputs, it can be optimized to correct isi on all those seven inputs through 16 different equalization choices. placing the tusb544 between a usb3.1 host/displayport 1.4 gpu and a usb3.1 type-c receptacle can correct signal integrity issues resulting in a more robust system. 8.2 typical application figure 34. tusb544 in a host application usb3.1/ dp1.4 host tusb544 type-c receptacle utx1n utx1p urx1n urx1p dtx1n dtx1p dtx2p dtx2n drx1p drx1n drx2p drx2n urx2p urx2n utx2p utx2n tx1n tx1p rx1n rx1p rx2p rx2n tx2p tx2n a b c f d e g h pcb trace of length x ab pcb trace of length x ef pcb trace of length x gh pcb trace of length x cd
40 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated typical application (continued) 8.2.1 design requirements for this design example, use the parameters shown in table 25 . table 25. design parameters parameter value a to b pcb trace length, x ab 12 inches c to d pcb trace length, x cd 12 inches e to f pcb trace length, x ef 2 inches g to h pcb trace length, x gh 2 inches pcb trace width 4 mils ac-coupling capacitor (75 nf to 265 nf) 100 nf vcc supply (3 v to 3.6 v) 3.3 v i2c mode or gpio mode i2c mode. (i2c_en pin != "0") 1.8v or 3.3v i2c interface 3.3v i2c. pull-up the i2c_en pin to 3.3v with a 1k ohm resistor. 8.2.2 detailed design procedure a typical usage of the tusb544 device is shown in figure 35 . the device can be controlled either through its gpio pins or through its i 2 c interface. in the example shown below, a type-c pd controller is used to configure the device through the i 2 c interface. in i 2 c mode, the equalization settings for each receiver can be independently controlled through i 2 c registers. for this reason, all of the equalization pins (ueq[1:0] and deq[1:0]) can be left unconnected. if these pins are left unconnected, the tusb544 7-bit i 2 c slave address will be 0x12 because both ueq1/a1 and ueq0/a0 will be at pin level "f". if a different i 2 c slave address is desired, ueq1/a1 and ueq0/a0 pins should be set to a level which produces the desired i 2 c slave address.
41 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 35. typical application circuit a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a12 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b1 gnd gnd gnd gnd txp2 txn2 vbus vbus vbus vbus urxp2 urxn2 sbu1 dn1 dp1 cc1 txn1 txp1 urxp1 urxn1 sbu2 cc2 dp2 dn2 drx2p drx2n dtx2p dtx2n dtx1n dtx1p drx1n drx1p sbu1 sbu2 auxp auxn tusb544 auxp auxn dp_pwr (3.3v) 100k 100k 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf usb 3.1/dp1.4 host usb type-c receptacle urx2p urx2n utx2p utx2n utx1n utx1p urx1n urx1p rx2p rx2n tx2p tx2n tx1n tx1p rx1n rx1p vcc 100nf 10uf 100nf 100nf 100nf vcc vcc vcc 2m 2m type-c pd controller r 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v r v i2c tp swap 3.3v 3.3v i2c_en ueq0/a0 ueq1/a1 hpdin cfg0 cfg1 deq0 deq1 slp_s0# flip/scl ctl0/sda ctl1 vio_sel gpio mode only connections 3.3 v 3.3v 3.3v dir0 dir1 gpio/i2c mode connections 3.3v copyright ? 2017, texas instruments incorporated
42 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.3 application curve figure 36. insertion loss of fr4 pcb traces frequency (ghz) insertion loss (db) 0 2 4 6 8 10 12 14 16 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 d009 length=12in, width=6mil length=16in, width=6mil length=20in, width=6mil length=24in, width=6mil length=4in, width=4mil length=8in, width=10mil length=8in, width=6mil
43 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3 system examples 8.3.1 usb 3.1 only (usb/dp alternate mode) the tusb544 will be in usb3.1 only when the ctl1 pin is low and ctl0 pin is high. figure 37. usb3.1 only ? no flip figure 38. usb3.1 only ? with flip type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated usb/dp source tusb544 sbu1 sbu2 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control hpd ctl flip 0 1 usb/dp sink pd controller d+/- hpd control ctl flip 0 1 tx1 rx1 d+/- cc1 cc2 tusb544 tx1 rx1 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 rx1 dir1/dir0/ctl1/ctl0/flip = l/l/l/h/l usb/dp source (usb only no flip) usb/dp sink (usb only no flip) dir1/dir0/ctl1/ctl0/flip = l/h/l/h/l tx1 rx1 auxp auxn type-c cable hpdin hpdin sbu1 sbu2 auxp auxn type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated usb/dp source tusb544 sbu1 sbu2 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control hpd ctl flip 0 1 dp/usb sink pd controller d+/- hpd control ctl flip 0 1 tx2 rx2 d+/- cc1 cc2 tusb544 tx2 rx2 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx2 dir1/dir0/ctl1/ctl0/flip = l/l/l/h/h usb/dp source (usb only flip) usb/dp sink (usb only flip) dir1/dir0/ctl1/ctl0/flip = l/h/l/h/h tx2 rx2 auxp auxn type-c cable hpdin hpdin sbu2 sbu1 auxn auxp
44 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated system examples (continued) 8.3.2 usb3.1 and 2 lanes of displayport figure 39. usb3.1 + 2 lane dp ? no flip figure 40. usb 3.1 + 2 lane dp ? flip type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated dir1/dir0/ctl1/ctl0/flip = l/l/h/h/h usb/dp source (usb + 2 lane dp flip) usb/dp sink (usb + 2 lane dp flip) dir1/dir0/ctl1/ctl0/flip = l/h/h/h/h usb/dp source tusb544 sbu1 sbu2 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control hpd ctl flip 0 1 pd controller d+/- hpd control sbu1 sbu2 ctl flip 0 1 tx2 tx1 rx2 rx1 d+/- cc1 cc2 tusb544 ml0 ml1 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx1 rx2 ml1 tx2 ml0 rx2 auxp auxn auxp auxn sbu1 sbu2 sbu2 sbu1 auxn auxp type-c cable auxn auxp tx2 rx2 usb/dp sink hpdin hpdin type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated usb/dp source tusb544 sbu1 sbu2 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control hpd ctl flip 0 1 pd controller d+/- hpd control sbu2 sbu1 ctl flip 0 1 tx2 tx1 rx2 rx1 d+/- cc1 cc2 tusb544 tx1 rx1 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx1 rx2 dir1/dir0/ctl1/ctl0/flip = l/l/h/h/l usb/dp source (usb + 2 lane dp no flip) usb/dp sink (usb + 2 lane dp no flip) dir1/dir0/ctl1/ctl0/flip = l/h/h/h/l tx1 ml1 rx1 ml0 auxp auxn auxp auxn sbu1 sbu2 sbu1 sbu2 auxp auxn type-c cable auxn auxp ml0 ml1 usb/dp sink hpdin hpdin
45 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated system examples (continued) 8.3.3 displayport only figure 41. four lane dp ? no flip figure 42. four lane dp ? with flip type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated usb/dp source tusb544 sbu1 dtx1 dtx2 drx1 drx2 sbu2 pd controller cc1 cc2 control hpd ctl flip 0 1 pd controller d+/- hpd control sbu1 sbu2 ctl flip 0 1 tx2 tx1 rx2 rx1 d+/- cc1 cc2 tusb544 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx1 rx2 dir1/dir0/ctl1/ctl0/flip = l/l/h/ l/h usb/dp source (4 lane dp flip) usb/dp sink (4 lane dp flip) dir1/dir0/ctl1/ctl0/flip = l/h/h/l/h ml1 ml2 ml0 ml3 auxp auxn auxp auxn sbu1 sbu2 type-c cable auxn auxp ml3 ml0 ml2 ml1 usb/dp sink hpdin hpdin sbu2 sbu1 auxn auxp type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated usb/dp source tusb544 sbu1 sbu2 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control hpd ctl flip 0 1 pd controller d+/- hpd control auxn auxp sbu1 sbu2 ctl flip 0 1 tx2 tx1 rx2 rx1 d+/- cc1 cc2 tusb544 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx1 rx2 dir1/dir0/ctl1/ctl0/flip = l/l/h/l/l usb/dp source (4 lane dp no flip) usb/dp sink (4 lane dp no flip) dir1/dir0/ctl1/ctl0/flip = l/h/h/l/l ml2 ml1 ml3 ml0 auxp auxn auxp auxn sbu1 sbu2 type-c cable ml0 ml3 ml1 ml2 usb/dp sink hpdin hpdin sbu1 sbu2 auxp auxn
46 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated system examples (continued) 8.3.4 usb 3.1 only (usb/custom alternate mode) figure 43. usb3.1 only ? no flip figure 44. usb3.1 only ? with flip type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated usb/custom source tusb544 sbu1 sbu2 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control hpd ctl flip 0 1 custom/usb sink pd controller d+/- hpd control ctl flip 0 1 tx2 rx2 d+/- cc1 cc2 tusb544 tx2 rx2 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx2 dir1/dir0/ctl1/ctl0/flip = h/l/l/h/h usb/custom source (usb only flip) usb/custom sink (usb only flip) dir1/dir0/ctl1/ctl0/flip = h/h/l/h/h tx2 rx2 auxp auxn type-c cable hpdin hpdin sbu2 sbu1 auxn auxp type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated usb/custom source tusb544 sbu1 sbu2 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control hpd ctl flip 0 1 usb/custom sink pd controller d+/- hpd control ctl flip 0 1 tx1 rx1 d+/- cc1 cc2 tusb544 tx1 rx1 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 rx1 dir1/dir0/ctl1/ctl0/flip = h/l/l/h/l usb/custom source (usb only no flip) usb/custom sink (usb only no flip) dir1/dir0/ctl1/ctl0/flip = h/h/l/h/l tx1 rx1 auxp auxn type-c cable hpdin hpdin sbu1 sbu2 auxp auxn
47 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated system examples (continued) 8.3.5 usb3.1 and 1 lane of custom alt mode figure 45. usb3.1 + 1 lane custom alt mode ? no flip figure 46. usb 3.1 + 1 lane custom alt. mode ? flip dir1/dir0/ctl1/0/flip = h/l/h/h/h usb/custom source (usb + 1 lane custom flip) usb/custom sink (usb + 1 lane custom flip) dir1/dir0/ctl1/0/flip = h/h/h/h/h usb/custom source tusb544 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control ctl flip 0 1 pd controller d+/- control ctl flip 0 1 tx2 tx1 rx2 rx1 d+/- cc1 cc2 tusb544 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx1 rx2 tx1 tx2 rx1 rx2 type-c cable usb/custom sink tx1 rx1 tx2 rx2 sbu1 sbu2 sbu1 auxp auxn auxp auxn sbu1 sbu2 auxn auxp sbu2 sbu1 auxn auxp hpdin hpdin hpd hpd type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated sbu2 usb/custom source tusb544 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control ctl flip 0 1 pd controller d+/- control ctl flip 0 1 tx2 tx1 rx2 rx1 d+/- cc1 cc2 tusb544 tx1 rx1 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx1 rx2 dir1/dir0/ctl1/0/flip = h/l/h/h/l usb/custom source (usb + 1 lane custom no flip) usb/custom sink (usb + 1 lane custom no flip) dir1/dir0/ctl1/0/flip = h/h/h/h/l tx1 tx2 rx1 rx2 type-c cable tx2 rx2 usb/custom sink sbu2 sbu2 sbu1 auxn auxp auxn sbu1 sbu2 auxn auxp hpdin hpdin hpd hpd type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated auxp sbu1 auxn sbu2 sbu1 auxp
48 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated system examples (continued) 8.3.6 usb3.1 and 2 lane of custom alt mode figure 47. two lane custom alternate mode ? no flip figure 48. two lane custom alternate mode ? with flip dir1/dir0/ctl1/ctl0/flip = h/l/h/h/h usb/custom source (usb + 2 lane custom flip) usb/custom sink (usb + 2 lane custom flip) dir1/dir0/ctl1/ctl0/flip = h/h/h/h/h usb/custom source tusb544 sbu1 sbu2 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control hpd ctl flip 0 1 pd controller d+/- hpd control sbu1 sbu2 ctl flip 0 1 tx2 tx1 rx2 rx1 d+/- cc1 cc2 tusb544 ln0 ln1 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx1 rx2 ln1 tx2 ln0 rx2 auxp auxn auxp auxn sbu1 sbu2 sbu2 sbu1 auxn auxp type-c cable auxn auxp tx2 rx2 usb/custom sink hpdin hpdin type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated usb/custom source tusb544 sbu1 sbu2 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control hpd ctl flip 0 1 pd controller d+/- hpd control sbu2 sbu1 ctl flip 0 1 tx2 tx1 rx2 rx1 d+/- cc1 cc2 tusb544 tx1 rx1 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx1 rx2 dir1/dir0/ctl1/ctl0/flip = h/l/h/h/l usb/custom source (usb + 2 lane custom no flip) usb/custom sink (usb + 2 lane custom no flip) dir1/dir0/ctl1/ctl0/flip = h/h/h/h/l tx1 ln1 rx1 ln0 auxp auxn auxp auxn sbu1 sbu2 sbu1 sbu2 auxp auxn type-c cable auxn auxp ln0 ln1 usb/custom sink hpdin hpdin type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated
49 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated system examples (continued) 8.3.7 usb3.1 and 4 lane of custom alt mode figure 49. four lane custom alternate mode ? no flip figure 50. four lane custom alternate mode ? with flip usb/custom source tusb544 sbu1 dtx1 dtx2 drx1 drx2 sbu2 pd controller cc1 cc2 control hpd ctl flip 0 1 pd controller d+/- hpd control sbu1 sbu2 ctl flip 0 1 tx2 tx1 rx2 rx1 d+/- cc1 cc2 tusb544 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx1 rx2 dir1/dir0/ctl1/ctl0/flip = h/l/h/l/h usb/custom source (4 lane custom flip) usb/custom sink (4 lane custom flip) dir1/dir0/ctl1/ctl0/flip = h/h/h/l/h ln1 ln2 ln0 ln3 auxp auxn auxp auxn sbu1 sbu2 type-c cable auxn auxp ln3 ln0 ln2 ln1 usb/custom sink hpdin hpdin sbu2 sbu1 auxn auxp type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated usb/custom source tusb544 sbu1 sbu2 dtx1 dtx2 drx1 drx2 pd controller cc1 cc2 control hpd ctl flip 0 1 pd controller d+/- hpd control auxn auxp sbu1 sbu2 ctl flip 0 1 tx2 tx1 rx2 rx1 d+/- cc1 cc2 tusb544 utx1 utx2 urx1 urx2 dtx1 dtx2 drx1 drx2 utx1 utx2 urx1 urx2 tx1 tx2 rx1 rx2 dir1/dir0/ctl1/ctl0/flip = h/l/h/l/l usb/custom source (4 lane custom no flip) usb/custom sink (4 lane custom no flip) dir1/dir0/ctl1/ctl0/flip = h/h/h/l/l ln2 ln1 ln3 ln0 auxp auxn auxp auxn sbu1 sbu2 type-c cable ln0 ln3 ln1 ln2 usb/custom sink hpdin hpdin sbu1 sbu2 auxp auxn type t c receptacle type t c receptacle copyright ? 2017, texas instruments incorporated
50 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 9 power supply recommendations the tusb544 is designed to operate with a 3.3 v power supply. levels above those listed in the absolute maximum ratings table should not be used. if using a higher voltage system power supply, a voltage regulator can be used to step down to 3.3 v. decoupling capacitors should be used to reduce noise and improve power supply integrity. a 0.1- f capacitor should be used on each power pin.
51 tusb544 www.ti.com sllsez0b ? april 2017 ? revised may 2017 product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 10 layout 10.1 layout guidelines 1. rxp/n and txp/n pairs should be routed with controlled 90-ohm differential impedance (+/- 15%). 2. keep away from other high speed signals. 3. intra-pair routing should be kept to within 2 mils. 4. length matching should be near the location of mismatch. 5. each pair should be separated at least by 3 times the signal trace width. 6. the use of bends in differential traces should be kept to a minimum. when bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be 135 degrees. this will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on emi. 7. route all differential pairs on the same of layer. 8. the number of vias should be kept to a minimum. it is recommended to keep the vias count to 2 or less. 9. keep traces on layers adjacent to ground plane. 10. do not route differential pairs over any plane split. 11. adding test points will cause impedance discontinuity; and therefore, negatively impacts signal performance. if test points are used, the test points should be placed in series and symmetrically. the test points must not be placed in a manner that causes a stub on the differential pair. 10.2 layout example figure 51. ac coupling capacitors aux urx2 drx1 utx2 utx1 urx1 dtx2 dtx1 drx2 sbu to usb type-c receptacle to usb host/gpu gnd
52 tusb544 sllsez0b ? april 2017 ? revised may 2017 www.ti.com product folder links: tusb544 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation the documents identified in this section are referenced within this specification. most references with the text will use a document tag, identified as [document tag], instead of the complete document title to simplify the text. for related documentation see the following: ? [usb31] universal serial bus 3.1 specification. ? [typec] universal serial bus type c cable and connector specification 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 13-may-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TUSB544Irnqr active wqfn rnq 40 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tusb544 TUSB544Irnqt active wqfn rnq 40 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tusb544 tusb544rnqr preview wqfn rnq 40 3000 tbd call ti call ti 0 to 70 tusb544rnqt preview wqfn rnq 40 300 tbd call ti call ti 0 to 70 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 13-may-2017 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TUSB544Irnqr wqfn rnq 40 3000 330.0 12.4 4.3 6.3 1.1 8.0 12.0 q2 TUSB544Irnqt wqfn rnq 40 250 180.0 12.4 4.3 6.3 1.1 8.0 12.0 q2 package materials information www.ti.com 14-may-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TUSB544Irnqr wqfn rnq 40 3000 367.0 367.0 35.0 TUSB544Irnqt wqfn rnq 40 250 210.0 185.0 35.0 package materials information www.ti.com 14-may-2017 pack materials-page 2
www.ti.com package outline c 40x 0.25 0.15 4.70.1 40x 0.5 0.3 0.8 max (0.2) typ 0.05 0.00 36x 0.4 2x 2.8 2x 4.4 2.70.1 a 6.1 5.9 b 4.1 3.9 wqfn - 0.8 mm max height rnq0040a plastic quad flatpack - no lead 4222125/b 01/2016 pin 1 index area 0.08 seating plane 1 8 21 28 9 20 40 29 (optional) pin 1 id 0.1 c a b 0.05 exposed thermal pad notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. scale 2.500
www.ti.com example board layout 0.05 min all around 0.05 max all around 40x (0.2) 40x (0.6) ( ) typ via 0.2 36x (0.4) (3.8) (5.8) 4x (1.1) (4.7) (r ) typ 0.05 (2.7) 2x (2.1) 6x (0.75) wqfn - 0.8 mm max height rnq0040a plastic quad flatpack - no lead 4222125/b 01/2016 symm 1 8 9 20 21 28 29 40 symm land pattern example scale:15x notes: (continued) 4. this package is designed to be soldered to a thermal pad on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271). solder mask opening metal under solder mask solder mask defined metal solder mask opening solder mask details non solder mask defined (preferred)
www.ti.com example stencil design 40x (0.6) 40x (0.2) 36x (0.4) (5.8) (3.8) 6x (1.3) 6x (0.695) 4x (1.5) (r ) typ 0.05 6x (1.19) wqfn - 0.8 mm max height rnq0040a plastic quad flatpack - no lead 4222125/b 01/2016 notes: (continued) 5. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. symm metal typ solder paste example based on 0.1 mm thick stencil exposed pad 73% printed solder coverage by area scale:18x symm 1 8 9 20 21 28 29 40
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own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2017, texas instruments incorporated

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